What does IP mean?
Generally, The IP in the chip industry is also called an IP core. It refers to the mature design of circuit modules with independent functions in the chip. The circuit module design can be applied to other chip design projects containing the circuit module. It can reduce the design workload, shorten the design cycle, and improve the success rate of the chip design. The mature design of the circuit module embodies the designer’s wisdom and reflects the designer’s intellectual property rights. Therefore, the chip industry uses the IP core (Intellectual Property Core) to represent the mature design of this circuit module.
A complex chip is a circuit part designed by the chip designer and connected to multiple purchased IP cores. As shown in Figure 1, to design a chip with such a structure, the design company can outsource all the IP cores (different color modules) in the chip. Only the part of the “design chip” that has self-designed (indicated in green).
The chip design process in the above figure is like the system circuit board development process in Figure 2. It is a process of layout, placement, and signal connection with an existing and mature IP core (or chip). We call this process a Multiplexing of IP cores (or chips). The difference is that in addition to the chip and the connection line on the system circuit board, system developers rarely develop their own chips. In the chip design process, the chip designer has to design a part of his own circuit and complete the signal connection between each part.
The origin of IP starts from the early chip design process. The integrated scale of the early chips was small and the design complexity was not high. The chip designers complete all the circuits on the chip independently. Chip companies with low design levels and limited capabilities can only design small and simple chips. Only chip companies with high design levels and strong capabilities can design large-scale chips with complex functions. In this period, no matter the chip scale is large or small, the chip company itself design the chip from the “head” to the “foot”. A few large international chip companies basically control the early high-end chips.
As the modern information society has higher requirements for chips, the scale of chips has increased exponentially, and the complexity has increased dramatically. It is almost impossible for small and medium chip companies to independently complete a complex chip design. Especially in the late 1980s, the foundry business model appeared in the chip industry. And a large number of small and medium-sized microchip design companies (Fabless) emerged. During this period, the chip design industry urgently needs to solve the problem that small chip companies cannot design large chips.
There are many enlightening ideas to solve this problem. For example building blocks and jigsaw drawing toys; designing large-scale machines from standard parts; calling and designing large-scale software by software subprograms (or middleware); building large-scale electronic systems with chips, etc. The idea is to reuse pre-designed mature components to build a more complex system, eliminating the need to consider the internal problems of the components, and simplifying the complexity; reusing components, reducing repetitive labor, and saving time; reusing components to improve the whole The success rate of complex system construction.
There are four main functions. One is to simplify the chip design, shorten the chip design cycle, and improve the success rate of complex chip design. The second is IP development and multiplexing technology that makes it possible for small companies to design large chips. The third, to enable system companies to design their own chips and to improve independent innovation capabilities and the independent intellectual property content of the entire system. The fourth is to enable chip design to get rid of the traditional IDM model and became an independent industry in the industry chain, which promoted the rapid development of the chip design industry.
At present, although many small and medium-sized microchip design companies have limited design capabilities and levels, in order to seize the market and shorten the chip design cycle, they will purchase many IP cores to complete their own chip design projects. The number of developers and providers in the industry is increasing and becoming more and more professional. Various functions and various types of IP cores continue to emerge. IP trading activities are becoming more and more common, and the transaction amount is getting larger and larger.
Types of IP
IP cores are classified into three levels of behavior, structure, and physical, corresponding to three types of IP cores. They are Soft IP Core, a Firm IP Core that completes structural description, and a Hard IP Core based on physical description and process verification.
- Soft IP Core: it is an independent functional circuit module with hardware description language (HDL). From the perspective of chip design, it has only undergone RTL-level design optimization and functional verification. It does not contain any physical realization information. Therefore, the soft core has nothing to do with the manufacturing process.
After the user purchases the IP soft core, the correct gate-level design netlist can be synthesized. Then the subsequent structural design can be carried out, which has great flexibility. With the help of EDA synthesis tools, users can easily integrate with other IP soft cores and self-designed circuit parts, and design chips with different performances according to various semiconductor processes.
- Firm IP Core: Its design level is between the IP soft core and the IP hard core. In addition to completing all the design of the IP soft core, it also completes the design links of gate-level circuit synthesis and timing simulation. Generally, it is provided to users in the form of a gate-level circuit netlist.
- Hard IP Core: It provides a mask-level circuit module at the final stage of circuit design. It is provided to users in the form of the final layout and routing netlist. IP hard core not only has the predictability of results, but also can optimize power consumption and size for a specific process or a specific provider.